|dc.description.abstract||This dissertation presents design and application of two popular frequency synthesizers, namely, the direct digital frequency synthesis (DDS) and phase lock loop (PLL) synthesis.
DDS is a digital technique for frequency synthesis, waveform generation, sensor excitation, and digital modulation/demodulation in modern communication systems. DDS provides many advantages including fine frequency-tuning resolution, continuous-phase switching and accurate matched quadrature signals. DDS can directly generate and modulate signal at microwave frequencies. A high-speed DDS can be significantly simplified the transceiver architecture. Thus the cost of radio and radar systems can be reduced considerably.
High speed DDS over GHz is demanding for wireless communication systems. This research proposes work on designing a high speed DDS chip with nonlinear DAC in Silicon Germanium (SiGe) process and using DDS as test pattern generator for analog circuitry built-in self test.
Nonlinear DAC is needed for high speed DDS for it replaces conventional ROM and linear DAC. The structure and system performance are analyzed with experimental data for a DDS with nonlinear DAC. Tradeoffs should be made to gain the best performance with feasible hardware implementation.
Spurious components in the DDS output spectrum introduced by the phase truncation are problems and delta-sigma modulators can be used either in phase or frequency domain to suppress in-band spurs. The formula deductions of delta-sigma modulation in both phase and frequency domain are presented and various delta-sigma modulators such
as MASH, feed-forward, feedback and error feedback have been implemented in both phase and frequency in a CMOS DDS chip and their performances are compared.
Circuit and layout designs using SiGe technology of DDS building blocks such as current mode logic (CML), 11-bit pipe-lined accumulator, 12-bit carry look-ahead accumulator, 1-1-1 Mash type delta-sigma modulator and a nonlinear DAC are discussed.
A DDS-based built-in-self-test (BIST) is presented for analogy circuit test. It uses DDS for test pattern generator (TPG) and a multiplier and accumulator as output response analyzer (ORA) and thus avoids traditional FFT-based spectrum analysis. Detail methods of frequency response and linearity test are introduced and verified by a field programmable gate array (FPGA) experimental results.
PLL is another important frequency synthesis for its small area and power consumption. Fractional-N type PLL can have a wide loop bandwidth and fast settling time. The fractional spurs are reduced by delta-sigma modulators with new coefficients that have less out-band noise in order to suppress the modulators output bit pattern. A 2.5 GHz fractional-N PLL is designed in silicon on insulator (SOI) technology for its full dielectric device isolation, less junction capacitances, lower average device threshold voltages and less body effect and source follower effect.||en_US