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dc.contributor.advisorDai, Fa Foster
dc.contributor.advisorJaeger, Richard C.en_US
dc.contributor.advisorNiu, Guofuen_US
dc.contributor.authorDeng, Wentingen_US
dc.date.accessioned2009-02-23T15:53:45Z
dc.date.available2009-02-23T15:53:45Z
dc.date.issued2007-08-15en_US
dc.identifier.urihttp://hdl.handle.net/10415/1389
dc.description.abstractThis thesis discusses design and applications of two main frequency synthesizers: direct digital frequency synthesis (DDS) and phase lock loop (PLL) synthesis. DDS is a quickly developed digital technique for frequency synthesis and waveform generation in modern communication systems. It provides many advantages including flexible phase and frequency adjustment, highly-stable and fast frequency conversion. A basic DDS system consists of three main building blocks: accumulator, sine look up table and a digital to analog converter (DAC). Actually the ROM for sine look-up table occupies the majority of the DDS area and limits its maximum operation frequency due to the delay through the multi-layer decoders. To reduce the power dissipation, a nonlinear DAC has been introduced to replace the ROM-look-up table and the linear DAC. In most modern wireless communication systems, digital modulations become more and more popular since it increases channel capacity, the ability to transmit and receives information with higher accuracy than an analog communication system in the presence of noise and distortion. One of the most important applications of DDS is used in the digital modulations. It is very easy and flexible to implement phase modulations and frequency modulations by changing the accumulator’s output or frequency control words respectively. PLL also has been played an important role in communication systems. Compare to DDS with the same operation speed, PLL consumes smaller area and less power but has a relatively narrow tuning range due to voltage control oscillator’s (VCO) --Y΄free running‘ [1]. And among kinds of PLLs, fractional-N PLL stands out clearly from others. It can have a wide loop bandwidth, fast settling time and small channel space. However the fractional spur is the drawback, it is even worse than in other PLL. In order to reduce the spurs, delta-sigma modulators was used to decrease the periodic disturbance without affecting the synthesizer’s function. It moves noise from in-band to out-band, which can be removed by following low-pass filter. A 5 GHz differential integer-N PLL is designed and fabricated in 0.5um Silicon Germanium technology. Circuit designs of main building blocks are discussed in details, such as phase detector, charge pump, 8 bit multi-modular divider with extension and programmable divider. And all digital blocks are used current-mode-logic (CML) for its high speed and relatively low power consumption.en_US
dc.language.isoen_USen_US
dc.rightsEMBARGO_NOT_AUBURNen_US
dc.subjectElectrical and Computer Engineeringen_US
dc.titleFrequency Synthesizer Designs and Their Applicationsen_US
dc.typeThesisen_US
dc.embargo.lengthMONTHS_WITHHELD:36en_US
dc.embargo.statusEMBARGOEDen_US
dc.embargo.enddate2012-02-23en_US


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