On-wafer S-parameter Measurement Using Four-port Technique and Intermodulation Linearity of RF CMOS
Type of DegreeDissertation
DepartmentElectrical and Computer Engineering
MetadataShow full item record
Accurate on-wafer characterization of CMOS transistors at extremely high frequencies, e.g. above 60GHz, becomes critical for RFIC designs and CMOS technology development for millimeter wave applications. Traditional two-step error calibration lumps the linear systematic errors as a four-port error adaptor between the perfect VNA receivers and the probe tips, and the distributive on-wafer parasitics as equivalent circuits with shunt and series elements. However, the distributive nature of on-wafer parasitics becomes significant, and the lumped equivalent circuits fail at frequencies above 50GHz. The distributive on-wafer parasitics is essentially a four-port network between the probe tips and the transistor terminals. This dissertation develops two general four-port techniques that can solve the on-wafer parasitics four-port network, and demonstrates their utility on a 0.13µm RF CMOS technology. One is an analytical solution solving the Y-parameters of the four-port parasitics network. The other one is a numerical solution solving the T-parameters of the four-port parasitics network. Even though the two four-port solutions are developed for on-wafer parasitics de-embedding at the very beginning, the two solutions do not make any reciprocal and symmetric assumptions of the solved four-port network, and can be used for single-step calibration which solves the four-port network between perfect VNA receivers and transistor terminals. In this case, both systematic errors and on-wafer parasitics are included in one four-port network, and can be removed in a single step. With switch error removed, single-step calibration can provide as accurate results as two-step calibration from 2-110GHz. Another topic that draws the attention of RFIC designers is the linearity (nonlinearity) of CMOS transistors. Experimental IP3 results on a 90nm RF CMOS technology are presented at different biasing voltages, different device width, and different fundamental frequencies. To understand the biasing, device width, and frequency dependence of IP3, a complete IP3 expression is developed using Volterra series analysis and nonlinear current source method. The investigation indicates that not only the 2nd and 3rd order nonlinear output conductance but also the cross terms are important for IP3 sweet spot and high VGS IP3 modeling. Guidelines to identify the IP3 sweet spot for large devices used in RFIC designs are provided.