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dc.contributor.advisorNiu, Guofu
dc.contributor.authorZhang, Tong
dc.date.accessioned2009-07-17T19:29:15Z
dc.date.available2009-07-17T19:29:15Z
dc.date.issued2009-07-17T19:29:15Z
dc.identifier.urihttp://hdl.handle.net/10415/1799
dc.description.abstractInvestigations into single event effect (SEE) induced charge collection in Silicon Germanium (SiGe) heterojunction bipolar transistors (HBT) are made through three-dimensional (3-D) device simulation. The transistor is constructed based on actual device. The results indicate that collector-substrate (CS) junction plays an important role due to the reverse biased CS junction. Therefore by adding a dummy collector to the HBTs, a recently published radiation hardening by design (RHBD) technique, the total collector collected charge can be reduced due to reduction of the diffusion charge collection at the intrinsic CS junction. At present, the single event upset (SEU) sensitivity is primarily characterized using the total amount of collector charge collected during an ion strike. This, however, may not be accurate, as the contributions of different charge collection processes are greatly influenced by external loading and the circuit topology. The individual impact of drift and diffusion charge collection at the collector-base (CB) and CS junctions on SiGe HBT current mode logic (CML) circuit SEU is examined. The CS junction diffusion charge collection has negligible impact on circuit SEU, despite its large charge collection magnitude. The CB drift charge collection is as important as the CS drift charge collection, even though its charge magnitude is much less, because the resulting current excitation appears between collector and base nodes, and hence is amplified. Using selective ion track placement in 3-D simulations, we further find that an ion track passing through the physical CS junction is much more effective in causing SEU than an ion track not passing through the CS junction. This is attributed to potential funneling and consequent large induced drift current magnitude, which is necessary for SEU of CML circuit. For emitter followers, the conventional hardening approach to minimize SEE is using a higher emitter biasing current as the emitter current determines output. This, however, is shown to not work at all with 3-D mixed mode simulations. Instead, it is the CB junction charge collection that dominates emitter output SEE, because CB junction charge collection determines the base voltage deviation, and the emitter output follows the base deviation. Therefore, the impedance and the electric field across the CB junction are the most important factors affecting emitter follower SEE. From the simulation results, the product of SEE induced base current and the base biasing impedance determines the amount of base voltage upset or deviation. For base biasing impedance values found in practical circuits, a smaller base biasing impedance should be used to reduce emitter output voltage SEE, as the emitter voltage upset tracks the base voltage upset.en
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dc.subjectElectrical Engineeringen
dc.titleImpact of Charge Collection Mechanisms on Single Event Effects in SiGe HBT Circuitsen
dc.typethesisen
dc.embargo.lengthNO_RESTRICTIONen_US
dc.embargo.statusNOT_EMBARGOEDen_US


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