This Is AuburnElectronic Theses and Dissertations

Embedded Soft-Core Processor-Based Built-In Self-Test of Field Programmable Gate Arrays




Dutton, Bradley

Type of Degree



Electrical Engineering


The exponential growth in the number of transistors on very large scale integration (VLSI) integrated circuits (ICs), coupled with increasing device interface bandwidth and new surface mount and low profile packaging technologies, have made testing of ICs increasingly difficult and costly at all levels of the testing process. Field programmable gate arrays (FPGAs) pose a particularly difficult problem for test engineers due to their programmable nature, overall size and complexity, limited number of inputs/outputs (I/O), and large number and variety of embedded cores. In addition to manufacturing defects, “soft” errors due to single event upsets (SEUs) have become a serious problem because of the increasing size of the configuration memory in FPGAs and shrinking design rules, even in fault-tolerant systems operating at ground level. Building on previous work, this thesis uses built-in self-test (BIST) as a solution to the testing problem for Xilinx Virtex-5 FPGAs. BIST configurations are presented for the configurable logic blocks (CLBs), I/O Tiles, and SEU detection/correction cores in Xilinx Virtex-5 FPGAs. In addition, this thesis presents a novel approach to BIST that uses a soft-core processor configured in the fabric of the device under test to perform reconfiguration of the resources under test, control the BIST execution, and perform fault diagnosis. This approach is particularly useful for in-system testing of FPGAs in fault-tolerant or high-reliability systems because it greatly reduces the amount and complexity of external hardware required for test. To combat the problem of “soft” errors due to SEUs that can occur in the FPGA configuration memory during normal operation, an approach for on-line detection and correction of SEUs in the configuration memory of Xilinx Virtex-4 and Virtex-5 FPGAs is also presented. While not entirely immune to SEU effects, this approach greatly reduces the probability of an SEU induced failure in the user logic, and no single error from an SEU can cause a complete system failure.