Development of a GPS Software Receiver on an FPGA for Testing Advanced Tracking Algorithms
Type of Degreethesis
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In this thesis, the development of an FPGA-based software GPS receiver with a special focus on advanced tracking algorithms is developed. The particular algorithms of note in this thesis are in a class known as vector tracking algorithms. Vector tracking GPS algorithms boast an increased immunity to interference and jamming and the ability to perform at low signal-to-noise ratios. Addition of an inertial device to the vector tracking algorithm is known as deep integration and further boosts these benefits. A trade study is presented that compares different hardware platforms for an embedded real-time system. An FPGA is chosen based on its ability to combine all of the necessary functions on a single device and its ability to seque a FPGA logic design to an application-specific integrated circuit (ASIC). Implementation details of each different component that constitutes a GPS receiver are given. In the single system, three soft-core microprocessors are synthesized on the FPGA to compute various components of the GPS algorithm, and their interfacing to other custom logic and to each other is described. The operation of each of the custom GPS logic modules is outlined in detail. Hardware resource utilization and computational timing results are also given. This thesis shows that a preliminary design of a real-time embedded GPS receiver capable of vector tracking is feasible, but there are more improvements to be made before deep integration is successful in real time.