|dc.description.abstract||Built-In Self-Test (BIST) offers a system the ability to test itself. Though it introduces inevitable extra cost for the added hardware, it also makes it possible to monitor, measure and calibrate the system on the fly as will shown. With BIST, the reliability of the overall system can be improved and the testing and maintenance cost be reduced. This dissertation discusses a proposed mixed-signal BIST architecture and the implementation of one of its key components ---- numerically controlled oscillator (NCO). The proposed BIST is composed of a NCO-based test pattern generator (TPG) and a selective spectrum analysis (SSA)-based output response analyzer (ORA). It utilizes the digital-to-analog converter (DAC) and analog-to-digital converter (ADC), which typically exist in a mixed-signal system, to interface the digital TPG and ORA with the analog device under test (DUT).
Theoretically the SSA-based ORA is equivalent to fast Fourier transform (FFT), but it only utilizes two digital multiplier/accumulators (MACs) and thus requires much less area overhead than the latter. Because of its ability to perform spectrum estimation, the SSA-based ORA is able to conduct a suite of the analog functional measurements such as frequency response, 1dB compression point (P1dB), 3rd-order interception point (IP3), etc.. Basically the SSA down converts the DUT's output at the frequency under analysis to DC by multiplication and filters out the non-DC spectrum by accumulation, but usually the non-DC spectrum cannot be removed completely and causes calculation errors. Though these errors can be reduced by increasing accumulation time, the convergence rate is so slow that it requires long test time to achieve a reasonable accuracy. Theoretical analysis proves that the non-DC calculation errors can be minimized in short test time by stopping the accumulation at the integer multiple periods (IMPs) of the frequency under analysis. However, due to the discrete nature of a digital signal, it is impossible to correctly identify every IMP when it occurs. Thus the concept of fake and good IMPs is introduced and the circuits to generate them are also discussed. According to their advantages and drawbacks, they are chosen for different analog measurements. Performance of the SSA-based ORA is analyzed in a systematical way and it is shown that the proposed IMP circuits can greatly improve the efficiency of the ORA in terms of test time, area overhead, and measurement accuracy.
The NCO is one of the key components in the proposed BIST architecture and employed in both TPG and ORA. A typical NCO consists of a phase accumulator and look-up table (LUT) to convert the linear output of the accumulator to a sine or cosine wave. However, as the size of the digital-to-analog converter (DAC) increases the hardware overhead of the traditional NCO increases exponentially. COordinate Rotation DIgital Computer (CORDIC) is an iterative algorithm which is able to calculate trigonometric functions via simple addition, subtraction and bit shift operations. As a result, the CORDIC size increases linearly with the size of the DAC. However, the traditional CORDIC algorithm requires many iterations to achieve a reasonable degree of accuracy which excludes its use as a practical means for high-speed and area-efficient frequency synthesizers when compared with other LUT ROM compression techniques. This dissertation proposes a partial dynamic rotating (PDR) CORDIC algorithm. The proposed algorithm minimizes the number of iterations it requires as well as the effort required to implement each iteration such that the CORDIC can be pipelined for per-clock-cycle generation of sine/cosine waveforms. In addition, the PDR CORDIC has a greater spur-free dynamic range (SFDR) and signal-to-noise-and-distortion (SINAD) than the traditional table methods used for NCO implementations.||en