Design of 3.33GHz CML Processor Datapath
Type of Degreethesis
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Almost a decade processor speed has been stuck at operating frequency 2-3GHz due to excessive power consumption of CMOS logic gate at higher frequency whereas predicted speed at present was 10-15GHz. This leads the idea of multi-core design in today's processor architecture. However it increases the communication overhead β and there exist data dependency which cannot fully exploit the advantage of many-core design. Further many core design is increasing number of dark silicon and number of core cannot be increased after certain limit. Therefore a novel approaches in processor design using CML logic gate has been proposed. Handcrafted 16-bit CML microprocessor datapath has been developed at operating frequency 3.33GHz using 130nm CMOS technology. With the same feature size, CMOS gate is incapable to operate beyond 1GHz whereas CML logic gates were optimized for 12GHz using bias current of 70% of peak f_t current with a logic swing of 600mV. Considering critical path delay, circuit has been slowed down to operate at 3.33GHz. All the processor components - decoder, mux, register file, ALU was deliberately handcrafted due to lack of analog synthesizer tool. Reported static power consumption of multi-cycle CML processor datapath is 41.264W. However it is not the best case and could have been reduced to 50% by implementing multi-input CML logic. Expected chip area is 2.2mm x 3.45mm and power density per unit area is 5.44µW/µm2. Estimated performance evaluated is 892 MIPS. Supply voltage used is 2.8V. CML logic was defined as, logic-1 = 2.8V and logic-0 = 2.2V. 1V reference voltage was used to constant bias the current source and reset signal uses 1.3V and 0.7V for high and low logics respectively. It has been observed that it is possible to realize ultra-high speed processor using existing technology with minimum power consumption in CML logic.