This Is AuburnElectronic Theses and Dissertations

Low Noise, Low Power Capacitive-Coupling Quadrature Voltage-Controlled Oscillator for Phase-Locked Loops




Zhao, Feng

Type of Degree



Electrical Engineering


This dissertation presents the analytical results and design details of two quadrature voltage-controlled oscillators (QVCO). It uses capacitive quadrature-coupling technique to couple two voltage-controlled oscillator (VCO) cores. The proposed capacitive-coupling QVCO (CC-QVCO) architecture provides the advantage of low phase noise performance and elimination of the bi-modal oscillation. Different from conventional quadrature-coupling mechanism with active devices, CC-QVCO utilizes noiseless capacitors to form QVCO allowing shaped gate voltage and reduced thermal noise. A differential Colpitts CC-QVCO with enhanced swing is proposed to offer excellent phase noise performance under a 0.6-V power supply. It achieves 4.5dB lower phase noise than its single-phase counterpart at 3-MHz offset. Optimized capacitive coupling combined with source inductive enhance-swing technique enables low power and low phase noise simultaneously. The QVCO achieves a measured phase noise of -132.3dBc/Hz @ 3MHz offset with a center frequency of 5.6GHz and consumes 4.2mW from a 0.6-V supply. This performance corresponds to a Figure-of-Merit (FoM) of 191.5dB. Due to the inherent phase shift in the proposed quadrature-coupling path, the problem associated with ±90º phase ambiguity between the quadrature outputs has been avoided. Capacitive-coupling technique is also applied to classic NMOS cross-coupled VCO with current tail to demonstrate its advantages over other quadrature-coupling technique. The problem of phase ambiguity for this QVCO has also been successfully avoided by the inherent leading phase shifter. Silicon implementations and measurement results of this CC-QVCO and another class-C mode top-series QVCO (TS-QVCO) for comparison have been discussed. The CC-QVCO has been fabricated in a 0.13µm CMOS technology and occupies an area of 1.0×0.35mm2. With 1.2-V supply voltage, it achieves 0.23-0.91° phase error in the frequency range of 4.3-5.27GHz. It demonstrates the effectiveness of the capacitive-coupling technique for wide frequency range quadrature signal generation and low phase noise performance. ΣΔ modulator based fractional-N PLL is widely used to produce frequency reference for wireless communication systems. Quantization noise caused by ΣΔ modulator will degrade the phase noise spectrum at the PLL output, and the situation becomes worse when the loop is nonlinear. Techniques and structures for noise improvement have been proposed to address the problem of noise degradation caused by ΣΔ modulator. Also included is the design of a wideband PLL with power optimized divider. An intuitive but useful power optimization methodology is proposed for dividers.