|The conventional approach, widely practiced in the industry today, for testing analog
circuits is to ensure that the circuit conforms to data-sheet limits on all its speciﬁcations.
However, such a speciﬁcation based test methodology suﬀers from high levels of test cost stemming
from long test-times on expensive test equipment. In recent years the situation has only worsened
with the advent of mixed signal systems on chip (SoC), to a point where analog circuit test cost
is often found to be as much as 50% of the total test cost in spite of analog portions occupying
less than 5% of the chip area.
To alleviate the analog circuit test cost problem, a number of techniques exist in the literature
that can be broadly classiﬁed as (a) fault-model based test or (b) alternate test. Fault model
based test techniques direct their tests to identify faults in circuit components much like their
digital circuit test counterparts resulting in a test approach that can be easily automated and
relies on readily available output measurements on inexpensive test equipment. On the other hand,
alternate test techniques test a circuit by building a regression model relating a few easily
observable output parameters as signatures of the circuit to the actual circuit speciﬁcation.
Both these test paradigms for analog circuit test, however, have limited industry accep- tance due
to a lack of conﬁdence in the defect level and yield loss that the test procedures can guarantee in
the face of high manufacturing process variation and low signal levels that are characteristic of
modern analog circuits. An important reason for the (typically) high defect level and yield loss
resulting from the use of either of these two test paradigms is the unavailability of easily
obtainable circuit outputs that are (a) suﬃciently sensitive to circuit component values and (b)
have a high degree of correlation with circuit speciﬁcations.
The main ob jective of this thesis is to design analog test signatures (and associated
test procedures) that are (i) sensitive enough to capture even small variations in circuit
components, and (ii) suﬃciently correlated to circuit speciﬁcations and yet obtainable at limited
or no additional hardware and input signal design eﬀort. Additional ob jectives of this thesis are
to: 1) Extend the use of the new signatures to diagnose faulty circuit components in analog
circuits. 2) Use the test signatures to distinguish faults resulting from defects caused by
manufacturing process related variations. 3) Evaluate the theoretical bounds on the achievable
defect level and the resulting yield loss of fault model based test procedures relying on these
The sensitivity of the proposed test signatures is enhanced by an exponential transforma- tion,
called V-Transform. The new test signatures and associated procedures are evaluated using three
metrics test time, defect level (test escapes), and yield loss. We analyze the proposed
signatures theoretically in addition to extensive computer simulations and hard- ware measurements
on common RF/analog circuits such as ﬁlters and low noise ampliﬁers. A representative result of
one of our experiments is as follows: For 400 low noise ampliﬁer circuits that were tested, we ﬁnd
that the proposed V-transform based signatures resulted in smaller test escape (≈ 2%) and yield
loss (≈ 3%) when compared to other prevailing alternate test or fault-model based test methods,
while signiﬁcantly reducing test time (by
as much as 50%) compared to the traditional speciﬁcation based test methods.