Built-In Self-Test of Programmable Resources in Microcontroller Based System-on-Chips

Abstract

System-on-Chip (SoC) implementations typically incorporate embedded Field Programmable Gate Array (FPGA) cores to take advantage of the programmable logic and routing resources provided by FPGAs. Testing the FPGA core typically requires numerous configuration downloads to completely test the various modes of operation of the programmable logic resources and the size of each configuration download file is large due to large amount of programmable resources. However, the ability to perform dynamic partial reconfiguration of the FPGA core from embedded processor core opens new opportunities for testing the FPGA using Built-In Self-Test (BIST). This thesis discusses the implementation of BIST for FPGA cores using partial dynamic reconfiguration from the embedded processor. As a result, all external configuration downloads are eliminated and replaced by one single processor program that programs the FPGA core for BIST, executes the BIST sequence, retrieves the BIST results, and executes diagnostic procedures to locate and identify faults detected by the BIST. Total testing time is improved by as much as a factor of 45 and a configuration memory storage requirement by as much as a factor of 83 by using dynamic partial reconfiguration compared to the traditional approach that requires BIST configuration downloads for every mode of operation of the programmable logic resources in the FPGA core of the Atmel AT94K series SoCs.