Dual-Threshold Voltage Design of Sub-Threshold Circuits
Type of Degreedissertation
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Threshold voltage of MOSFET technology represents the value of the gate-source voltage when the current in a MOS transistor starts to increase significantly since the conduction layer just begins to appear. However, a MOSFET transistor can also function correctly with a supply voltage below its threshold voltage (Vth), which is referred to as sub-threshold operation or weak-inversion of a transistor. The circuits that works under a supply voltage in the sub-threshold range are named sub-threshold circuits. Due to the increasing emergence of energy-constrained electronic devices, it is more important to suppress energy consumption to achieve a longer battery life. Therefore there are demands for design methods for less energy consumption. Sub-threshold circuit provides a potential solution since it can reduce energy per cycle significantly by the scaling of supply voltage (Vdd) below threshold voltage (Vth). In addition, sub-threshold circuits are expected to receive increasing attention in the coming years since the minimum energy CMOS operation typically occurs when supply voltage scales down to the sub-threshold range. The dual-threshold voltage method benefits from the characteristics of low and high threshold voltages. Higher threshold voltage results in less leakage current, therefore less leakage power consumption with the sacrifice of delay. On the contrary, lower threshold voltage brings more leakage power consumption with faster speed. Dual-threshold voltage design is a common method for reducing leakage power consumption for above-threshold circuits. In this thesis, dual-threshold voltage is proven effective for reducing energy consumption per cycle (EPC) of sub-threshold circuits. It is demonstrated in this research that the energy per cycle is independent of threshold voltage in single-Vth designs.A dual-threshold voltage framework written in PERL language is developed to generate the optimal dual-threshold voltage design with minimum energy consumption. The proposed framework is built on a gate-slack based dual-threshold voltage algorithm to precisely find out the optimal high threshold voltage and supply voltage (Vddopt), along with accurate estimation of energy consumption for the generated dual-Vth designs. Meanwhile, the framework conducts static timing analysis (STA) to ensure that the dual-threshold voltage design is able to run at the fastest possible operating frequency at Vddopt. Experimental results on 32-bit ripple carry adder (RCA), 4-by-4 multiplier and ISCAS85 benchmark circuits show that minimum EPC is lowered by 10% to 29% by dual-Vth design over its single-Vth version. The impact of process variations is also discussed. Applying random process variations on threshold voltage as Gaussian variables can bring variations on both energy consumption and performance for sub-threshold circuits.