|dc.description.abstract||Analog multipliers are used in communication circuits, neural networks as well as frequency doublers, RMS circuits and phase detectors. High linearity is the prime issue for multipliers in conventional applications like modulation circuits. Power consumption is the criteria in case of massive parallel processing based neural networks. This thesis details the design process of four-quadrant multiplier designed using AMIS C5F CMOS process which could able to address the challenges mentioned above. Initially, different multiplier architectures are reviewed. A MOS resistor based multiplier and divider circuits are designed and simulated. Eliminating the limitations of this configuration, final four-quadrant multiplier is designed. In addition to these, input signal range, bandwidth, mismatching of transistors and active area of the chip are also optimized.
The final design of multiplier has ±2.2V input range, 73MHz bandwidth, 0.242mW power consumption with 10µA bias current and -63db total harmonic distortion at 100 KHz 1Vp-p input signal. Special layout techniques like interdigitation and common centriod methods are used to reduce mismatches between transistors and effects of process variations are minimized.||en_US