This Is AuburnElectronic Theses and Dissertations

Stress Analysis in Bipolar Transistors

Date

2016-05-03

Author

Gnanachchelvi, Parameshwaran

Type of Degree

Dissertation

Department

Electrical Engineering

Restriction Status

EMBARGOED

Restriction Type

Full

Date Available

04-25-2021

Abstract

Stress effects in semiconductor devices have gained significant attention in semiconductor industry nowadays. Stress effect in semiconductor devices is used as a beneficial effect in sensor applications and strain engineering and efforts are taken to increase these effects. Strain engineering is widely used for MOSFETs. Performance of SiGe based heterostructure bipolar transistors (HBTs) is improved by bandgap and strain engineering. However this approach is not fully developed for Si bipolar junction transistors (BJTs). While stress effects are useful in some areas there are some unwanted stress effects as well. The unintentional stresses developed during fabrication, processing and packaging are harmful in semiconductor devices and efforts are taken to mitigate these stress effects. In this research work, stress-induced changes were investigated in the perspective of improvement for strain engineering in Si BJTs as well as mitigation of stress effects in precision analog circuits. npn and pnp BJTs on (100) and (111) planes were studied using experimental and modeling approaches. Modeling approach was mainly used for this study in order to overcome the practical difficulties associated with fabrication of devices with different orientation and sizes and controlled application of stress in various orientations for measurements. Measurements were taken for in-plane normal stress and the validity of the model was verified. A new one-dimensional numerical model was developed in Matlab in order to make the stress analysis easier and more in-depth with short running time. Simulation results of the 1-D model and Sentaurus TCAD tool were compared and both results showed very good agreement. While commercial TCAD tools usually takes tens of minutes for 2-D or hours for 3-D simulations for this type of stress analysis, the newly developed 1-D model gives comparable results in seconds and without any loss of information generated. This model can be used for fast stress analysis/prediction in vertical or lateral npn/pnp BJTs in any plane and will help in developing optimal design for strain engineering in BJTs or stress mitigation in analog circuits. The stress induced changes in vertical and lateral bipolar transistors on (100) plane were quantitatively analyzed for different stress orientations. Our analysis revealed that for a vertical npn transistor substantial enhancement in collector current (IC), dc current gain, cutoff frequency (fT), and maximum oscillation frequency (fmax) can be achieved using an uniaxial in-plane compressive or an out-of-plane tensile stress. In a vertical pnp considerable improvement in IC can be achieved with an in-plane or an out-of-plane compressive stress while the changes in dc current gain, fT and fmax are minimal. Lateral pnp BJTs showed much higher improvement for in-plane longitudinal compressive stress. In addition, lateral npn BJTs showed higher improvement for out-of-plane compressive stress. These results revealed a promising opportunity for strain engineering in both vertical and lateral Si BJTs. This study also revealed that the transport limited BJTs are less sensitive to stress than injection limited BJTs. In addition, vertical pnp on (100) silicon is less sensitive to stress than the vertical npn on (100) plane or vertical npn or pnp on (111) plane. On (111) silicon vertical npn BJTs are less sensitive than the vertical pnp BJTs. Finally, stress effects in precision analog circuits have been explored with the help of Spice simulations incorporating the 1-D theoretical model. Some methods for stress mitigation in precision analog circuits are also suggested including usage of less sensitive BJTs whenever possible, keeping the matching BJTs in close proximity to avoid stress gradients, avoiding high stress regions in chips, usage of enclosed lateral devices for stress compensation.