Simulation Modeling and Analysis of Printed Circuit Board Assembly Lines

Abstract

This thesis focuses on simulation modeling and analysis of printed circuit board assembly lines. The objectives of the study include assessing the feasibility of process flow logic and relative impact of changing line configurations. It is aimed to identify constraints or bottlenecks and development of improvement strategies accordingly. Additionally, complex interactions between various resources are examined to identify effective operator allocation and allocate buffer space. A six-step methodology is developed for this purpose. PCB assembly template is used for simulation modeling in Arena 7.01. We introduce a unique method of integrating the resource state graph into simulation modeling for PCB assembly lines and analyzing it to identify constraints, bottlenecks, and potential for improvement in terms of throughput and operator allocation.