This Is AuburnElectronic Theses and Dissertations

RF Characterization and Modeling of 14nm RF FinFETs

Date

2019-12-04

Author

Zhang, Jiabi

Type of Degree

PhD Dissertation

Department

Electrical and Computer Engineering

Restriction Status

EMBARGOED

Restriction Type

Auburn University Users

Date Available

12-03-2024

Abstract

This work focuses on the characterization and compact modeling of RF characteristics of both n- and p-channel transistors fabricated using 14-nm FinFET technologies. DC I-V, as well as its higher order derivatives, C-V, S-parameters and two-tone intermodulation linearity are experimentally measured and modeled using BSIM-CMG compact model. Third order intermodulation distortion is examined using experimental measurements, circuit simulation with BSIM-CMG, and Volterra series analysis. Linearity sweet spots with respect to gate voltage and input power, as well as drain voltage dependence, are examined. A strategy for extracting BSIM-CMG model parameters for fitting intermodulation in addition to DC I-V, C-V and S-parameters is developed and demonstrated. Key BSIM-CMG model parameters are identified for simultaneously fitting DC I-V, C-V, Y-parameters and intermodulation distortion. Volterra series analysis shows that distortions resulting from $V_{DS}$ dependence of $I_{DS}$ well dominate over distortions from $V_{GS}$ dependence of $I_{DS}$. Third order intercept gate voltage ($V_{GS,IP3}$) is extracted from frequency dependence of IIP3. A worst case $V_{GS,IP3}$ of 0.5V is observed, compared to 0.7V in a 28-nm high-k metal gate planar device. Comparison is made between NMOS and PMOS on DC and RF characteristics. Compared to NMOS, PMOS shows larger $I_{DS}$, $g_m$ and $g_{o}$, comparable $f_T$, lower $f_{max}$ at minimum length, better IP3 over a large bias range, and a lower distortion at higher RF power. A larger $V_{GS,IP3}$ is observed in PMOS at higher $V_{GS}$ when $V_{DS}$ is relatively high.