Design and Implementation of High Performance Pipelined SAR ADC for Wireless Communications

Abstract

As the process keeps scaling down, successive approximation register (SAR) architecture becomes an attractive candidate in low-power, moderate-speed A/D converter (ADC) due its mostly digital operation. For high speed application, pipelining and SAR are combined to further improve the speed. As the bottleneck in traditional pipeline ADC, the associated residue generation and amplification continues to be extensively researched to achieve higher resolution. This work presents a dual-residue pipelined successive approximation register (SAR) A/D converter (ADC) architecture that relaxes the accuracy requirement for residue amplifications to fully utilize the benefits of power efficiency and technology scalability based on zero-crossing (ZX) only signals. The dual-residue architecture is illustrated with design of an 11b two-step pipelined ADC consisting of 8b coarse and 5b fine (with 2b over-range) SAR sub-ADCs, which resolve 2b and 1b per SAR conversion cycle, respectively. Two ZX signals (or dual-residues) in opposite polarities automatically available in each 2b SAR cycle are sampled and held at the end of the coarse conversion for use as the full-scale (FS) reference for the fine SAR that quantizes a fixed input of zero. An on-chip foreground offset calibration circuit is proposed and implemented to correct the offset mismatch in the dual residues. Simulation and measurement results are provided to demonstrate the operation and performance of the proposed ADC architecture. This work also discussed the continuous time analog low pass filter which is usually placed in front of ADC to prevent aliasing. Operational transconductance-C filter and active-RC filter are explored and designed. The simulation and measurement results are provided to demonstrate the functionality and performance.