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Browsing by Author "Stroud, Charles"
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Alternative Techniques for Built-In Self-Test of Field Programmable Gate Arrays
Newalkar, Aditya (2005-08-15)
In the Built-In Self-Test method of testing the logic and interconnect resources of the Field Programmable Gate Arrays (FPGAs), configuration time and time to retrieve of the test results dominate the duration of the test. ...
Analysis and Implementation of Built-In Self-Test for Block Random Access Memories in Virtex-5 Field Programmable Gate Arrays
Dailey, Justin (2011-07-18)
In order to ensure the proper operation of the embedded Block Random Access Memories (BRAMs) in Xilinx Virtex-5 Field-Programmable Gate Arrays (FPGAs) a dependable and resource efficient test is needed so that the integrity ...
Analysis and Improvement of Virtex-4 Block RAM Built-In Self-Test and Introduction to Virtex-5 Block RAM Built-In Self-Test
Garrison, Brooks (2009-04-27)
A reliable method for testing embedded memories within Virtex-4 and Virtex-5 Field-Programmable Gate Arrays (FPGAs) is needed by the current FPGA community. A method for testing the Virtex-4 embedded Block Random Access ...
Built-In Self Test for Regular Structure Embedded Cores in System-on-Chip
Garimella, Srinivas (2005-05-15)
Miniaturization and integration of different cores onto a single chip are increasing
the complexity of VLSI chips. To ensure that these chips operate as desired, they
have to be tested at various phases of their development. ...
Built-In Self Test of Configurable Memory Resources in Field Programmable Gate Arrays
Milton, Daniel (2007-12-15)
Testing embedded memory resources in Field Programmable Gate Arrays (FPGAs) is difficult because the collective signal fan-in and fan-out is much greater than the available external I/O. A testing approach is needed that ...
Built-In Self-Test Configurations for Field Programmable Gate Array Cores in Systems on Chip
Harris, Jonathan (2004-12-15)
Built-In Self-Test configurations for the logic and routing resources present in the
Field Programmable Gate Array core of a System-on-Chip is presented in this Thesis.
These configurations completely test the Programmable ...
Built-In Self-Test for Digital Signal Processor Cores in Virtex-4 and Virtex-5 Field Programmable Gate Arrays
Pulukuri, Mary (2010-05-04)
Current Field Programmable Gate Arrays (FPGAs) incorporate special cores, apart from logic, such as digital signal processor (DSP) cores. The DSP cores can be cascaded to implement complex functions. An effective test ...
Built-In Self-test for Input/Output Cells in Field Programmable Gate Arrays
Vemula, Sudheer (2006-08-15)
Programmable Input/Output (I/O) cells are an integral part of any Field Programmable Gate Array (FPGA). The resources associated with the programmable I/O cells are increasing as newer architectures of FPGAs are being ...
Built-In Self-Test for Input/Output Tiles in Field Programmable Gate Arrays
Lerner, Lee (2008-05-15)
Very large scale integration (VLSI) circuits use input/output (I/O) cells to both send and receive signals from external resources. Field Programmable Gate Arrays (FPGAs) and System-on-Chips (SoCs) with FPGA cores offer ...
Built-In Self-Test for the Analysis of Mixed-Signal Systems
Starr, George (2010-04-08)
A new Built-In Self-Test technique called Selective Spectrum Analysis has been developed for the measurement of analog characteristics in mixed-signal circuits. This design utilizes digital components to generate and collect ...
Built-In Self-Test of Global Routing Resources in Virtex-4 FPGAs
Yao, Jia (2009-05-05)
It is important to test programmable routing resources in Field Programmable Gate Arrays (FPGAs) because they take up the largest portion of configuration memory bits. In Virtex-4 FPGAs, routing resources account for over ...
Built-In Self-Test of Logic Resources in Field Programmable Gate Arrays Using Partial Reconfiguration
Dhingra, Sachin (2006-08-15)
Field Programmable Gate Arrays (FPGAs) are programmable logic devices that can be used to implement virtually any digital circuit design. Built-In Self-Test (BIST) is a testing approach that enables the device to test ...
Built-In Self-Test of Programmable Resources in Microcontroller Based System-on-Chips
Sunwoo, John (2005-12-15)
System-on-Chip (SoC) implementations typically incorporate embedded Field Programmable Gate Array (FPGA) cores to take advantage of the programmable logic and routing resources provided by FPGAs. Testing the FPGA core ...
Built-In Self-Test of the Programmable Interconnect in Field Programmable Gate Arrays
Dixon, Bobby (2008-12-15)
Testing programmable interconnect resources in Field Programmable Gate Arrays (FPGAs) is difficult because of the large number of wire segments and switches that must be tested. The adoption of Built-In Self-Test (BIST) ...
Delay Test Scan Flip-flop (DTSFF) Design and Its Applications for Scan Based Delay Testing
Xu, Gefu (2007-12-15)
Scan based delay testing is currently mostly implemented using launch-on-capture (LOC) delay tests. Launch-on-shift (LOS) tests are generally more effective, achieving higher fault coverage with significantly fewer test ...
Embedded Soft-Core Processor-Based Built-In Self-Test of Field Programmable Gate Arrays
Dutton, Bradley (2010-02-05)
The exponential growth in the number of transistors on very large scale integration (VLSI) integrated circuits (ICs), coupled with increasing device interface bandwidth and new surface mount and low profile packaging ...
Evaluating the Digital Fault Coverage for a Mixed-Signal Built-In Self-Test
Lusco, Michael (2011-11-21)
This thesis focuses on a digital Built-in Self-Test (BIST) approach to perform specification-
oriented testing of the analog portion of a mixed-signal system. The BIST utilizes a direct
digital synthesizer (DDS) based ...
Frequency Syntheses with Delta-Ssigma Modulations and their Applications for Mixed Signal Testing
Yang, Dayu (2006-12-15)
This dissertation presents design and application of two popular frequency synthesizers, namely, the direct digital frequency synthesis (DDS) and phase lock loop (PLL) synthesis.
DDS is a digital technique for frequency ...
Hierarchical Fault Collapsing for Logic Circuits
Sandireddy, Raja-Kiran-Kumar (2005-05-15)
The process of grouping stuck-at faults into equivalence or dominance classes and
then selecting one representative for each class is known as fault collapsing. There
have been several techniques to collapse the faults ...
Independence Fault Collapsing and Concurrent Test Generation
Doshi, Alok (2006-05-15)
The objective of this work is to find suitable targets for Automatic Test Pattern Generation (ATPG) such that a minimal test set is obtained for a combinational circuit. Original concepts of independence fault collapsing ...