Browsing by Author "Agrawal, Vishwani"

Now showing items 21-33 of 33

Minimizing N-Detect Tests for Combinational Circuits

Kantipudi, Kalyana (2007-05-15)

An N-detect test set detects each stuck-at fault by at least N different vectors. N-detect tests are of practical interest because of their ability to improve the defect coverage. The main problem that limits their use is ...

Net Diagnosis Using Stuck-at and Transition Fault Models

Zhao, Lixing (2011-11-02)

As deep sub-micron technologies are widely adopted in modern VLSI design and fabrication process, the shrinking size and increasing complexity of digital circuits make it more difficult to maintain a high yield. Diagnosis ...

Novel Approaches for Microelectronics Security and Test

Zhou, Ziqi (2021-08-05)

Due to the globalization in semiconductor industry, the cost of maintaining a foundry is enormous. Hence, most integrated circuit (IC) design houses have become fabless. Typically, a design house acquires multiple third ...

Novel Test Point Insertion Applications in LBIST

Sun, Yang (2021-11-15)

Pseudo-random stimulus for digital test is an established industry practice due to its simplicity and significant fault coverage. However, when applied to modern circuits, pseudo-random stimulus can fail to excite and ...

Polynomial-Time Algorithms for Designing Dual-Voltage Energy Efficient Circuits

Allani, Mridula (2011-11-14)

In this work, we propose a technique to use dual supply voltages in digital designs in order to get a reduction in energy consumption. Three new algorithms are proposed for nd- ing and assigning low voltage in dual ...

Power-Aware System-on-Chip Test Optimization through Frequency and Voltage Scaling

Sheshadri, Vijay (2014-04-29)

A System-on-Chip (SoC) is a complete system that has been integrated onto a single chip. An SoC is often designed by embedding reusable blocks called cores. With shrinking device sizes, SoC cores are growing in number and ...

Pre-bond TSV Test Optimization and Stacking Yield Improvement for 3D ICs

Zhang, Bei (2014-12-10)

Through silicon via (TSV) based three-dimensional IC (3D IC) exhibits various advantages over traditional two-dimensional IC (2D IC), including heterogeneous integration,reduced delay and power dissipation, compact device ...

Reducing ATE Test Time by Voltage and Frequency Scaling

Venkataramani, Praveen (2014-03-20)

During wafer sort, the fabricated chips are subjected to tests that verify if they meet the design specification. Test application time plays a critical role while verifying large volume of dice in a given period of time. ...

Secondary Bus Performance in Reducing Cache Writeback Latency

Venkatesh, Rakshith (2011-04-08)

For single as well as multi core designs, effective strategies to minimize cache access latencies have been proposed by a number of researchers over the last decade. Such designs include the Miss Status Holding Registers, ...

Stress Analysis in Bipolar Transistors

Gnanachchelvi, Parameshwaran (2016-05-03)

Stress effects in semiconductor devices have gained significant attention in semiconductor industry nowadays. Stress effect in semiconductor devices is used as a beneficial effect in sensor applications and strain engineering ...

Testing and Diagnosis of CMOS Open Defects in the Presence of Common Hazards

Han, Chao (2015-07-29)

CMOS open defects are breaks in wires or defective transistors within some library cell causing pull up or pull down failure of the defective gates. Traditionally, TSOF (transistor stuck-open fault) is used to model such ...

Towards Unclonable System Design for Resource-Constrained Application

Mahmod, Md Jubayer al (2019-07-01)

As we forge ahead to achieve the targeted connectivity among devices in this Internet of Things (IoT) era, reliability and security of individual device have become a matter of paramount importance. Cloned electronic ...

Ultra Low Power CMOS Design

Kim, Kyungseok (2011-05-05)

The ubiquitous era of emerging portable devices demands long battery lifetime as a primary design goal. Subthreshold circuit design can reduce energy per cycle in an order of magnitude of nominal operating circuits by ...