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Built-In Self-Test for Input/Output Tiles in Field Programmable Gate Arrays


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dc.contributor.advisorStroud, Charles
dc.contributor.advisorAgrawal, Vishwani D.en_US
dc.contributor.advisorNelson, Victoren_US
dc.contributor.authorLerner, Leeen_US
dc.date.accessioned2008-09-09T22:34:31Z
dc.date.available2008-09-09T22:34:31Z
dc.date.issued2008-05-15en_US
dc.identifier.urihttp://hdl.handle.net/10415/1071
dc.description.abstractVery large scale integration (VLSI) circuits use input/output (I/O) cells to both send and receive signals from external resources. Field Programmable Gate Arrays (FPGAs) and System-on-Chips (SoCs) with FPGA cores offer increasingly complex I/O cell resources with new generations of device architectures. I/O cells can often be grouped together to form I/O tiles that can support even more complex features. The ever increasing complexity of I/O tiles is indicative of the need for a reliable testing methodology to ensure the functionality of device resources. Built-in self-test (BIST) is one such testing methodology that incorporates the testing circuitry with the device under test. A total of 78 BIST configurations are developed to test the I/O tile logic resources and supported I/O standards in Xilinx Virtex-4 FPGAs. The BIST configurations are implemented and verified on Virtex-4 FPGAs. The BIST configurations are generated for all Virtex-4 FPGAs. The general BIST approach presented in this thesis is applicable to any FPGA or SoC with a FPGA core. The BIST approach can be used for both manufacturing and system level testing for I/O tiles with both bonded and unbonded I/O buffers.en_US
dc.language.isoen_USen_US
dc.subjectElectrical and Computer Engineeringen_US
dc.titleBuilt-In Self-Test for Input/Output Tiles in Field Programmable Gate Arraysen_US
dc.typeThesisen_US
dc.embargo.lengthNO_RESTRICTIONen_US
dc.embargo.statusNOT_EMBARGOEDen_US

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