Design and Implementation of High-Speed Low-Power Analog-to-Digital and Digital-to-Analog Converters

Abstract

With the rapid development of modern communication and personal wireless products, there are increased demands for next generation communication transceivers that feature ultra-high data conversion rates with reconfigurable architectures. As the essential building block in most communication and control system, data converters, including analog-to-digital converter (ADC) and digital-to-analog converter (DAC), are serving as the link between analog and digital worlds. Featuring high sampling rate, low power supply voltage and low power consumption, next generation data converters in transceivers will be architecturally closer to the signal interface, antenna. By digitizing the received signal or converting digital code back to analog signal at ultra-high frequency instead of baseband frequency or intermediate frequency, RF transceivers can significantly simplify the radio architecture. For example, as for high-speed ADC, moving as many of the radio functions from the RF transceiver IC to the baseband digital chip as possible will improve the radio performance, cut the overall power and, most importantly, allow re-configurability of the radio designs for multi-band and multi-standard coexistence. In this research, multiple ADC/DAC designs are implemented in different technologies to address either high-speed or low-power design challenges or even both. Circuit design techniques and considerations are extensively and carefully discussed in both architectural and transistor level. Simulation and measurement results are also given to verify functionality and performance of proposed designs. For 3-bit over X-band high-speed ADCs, 0.12um SiGe HBT technology featured with ft/fmax of 210/310 GHz is used to enhance the device operation speed. CML circuits are employed for digital logic implementation to provide fast switching speed. For 12-bit low power high speed pipeline ADCs, low supply voltage is applied to reduce the overall power consumption. In addition, sharing operational amplifiers (OpAmp) between two time-interleaved pipeline ADC channels is used to further save power and double sampling rate. For 12-bit cryogenic DAC, current steering architecture is utilized to maintain a good trade-off between high-speed and low-power. 6+4+2 bit segmentation scheme is to keep the best balance between minimizing the circuit area of thermometer decoders and optimizing the DAC static and dynamic performance.