Energy Efficiency and Process Variation Tolerance of 45 nm Bulk and High-k CMOS Devices
Metadata Field | Value | Language |
---|---|---|
dc.contributor.advisor | Agrawal, Vishwani D. | |
dc.contributor.author | Venkatasubramanian, Muralidharan | |
dc.date.accessioned | 2011-04-18T19:00:27Z | |
dc.date.available | 2011-04-18T19:00:27Z | |
dc.date.issued | 2011-04-18 | |
dc.identifier.uri | http://hdl.handle.net/10415/2537 | |
dc.description.abstract | With transistor sizes being reduced to sub 45nm ranges, we have seen an improvement in speed, better performance, and deeper integration of digital circuits. However, there has been a corresponding increase in power consumption, along with greater energy dissipation. The reason is because of increased leakage current in the channel. A proposed solution is a shift towards high-k materials and metal gate from poly-silicon gate of yesteryear. Reduced feature sizes also suffer from greater parametric process variations during lithography and cause identical circuits to behave differently. With high-k technology overshadowing bulk technology ever since transistor sizes hit 45nm, a greater understanding of how the properties of high-k technology will affect digital devices especially their speed, power consumption, and energy dissipated upon voltage scaling is needed. Also, a better estimation of effects of parametric variations on circuits designed in high-k technology can provide valuable information which can be used to improve current designs. | en_US |
dc.rights | EMBARGO_NOT_AUBURN | en_US |
dc.subject | Electrical Engineering | en_US |
dc.title | Energy Efficiency and Process Variation Tolerance of 45 nm Bulk and High-k CMOS Devices | en_US |
dc.type | thesis | en_US |
dc.embargo.length | NO_RESTRICTION | en_US |
dc.embargo.status | NOT_EMBARGOED | en_US |