This Is AuburnElectronic Theses and Dissertations

Implementation of High Speed SAR ADC with Proposed Efficient DAC Architecture




Zhao, Haoyi

Type of Degree

Master's Thesis


Electrical and Computer Engineering


A novel, high performance SAR ADC architecture is designed and fabricated in 130nm SiGe technology and 45nm soi technology. In the beginning fundamentals of ADC (Analog-to-Digital Convertor) are introduced and several types of ADC are studied, followed by concepts and details of SAR ADC (Successive Approximation ADC), which consists of sample and hold component, DAC, analog comparator, and SAR logic component. In this paper, the architectures and design details of DAC will be focused, while the design flow and details of other components will be briefly mentioned. The DAC architectures aiming at high speed switching, low power consumption, and minimized mismatch are proposed and fabricated into the whole ADC system. After that the measurements of the 1st fabrication version is presented and analyzed.