|dc.description.abstract||This paper presents the analysis, design, simulation, and test results for a Fractional-N
PLL frequency synthesizer. The synthesizer is designed to cover multiple frequency bands,
require low power, and have low noise. Detailed analysis is presented on loop dynamics,
stability, and noise. All components in the circuit are designed for low noise and low power.
For example, The Multi-Modulus Divider (MMD) is implemented such that it has the
minimum number of gates and the lowest power consumption. The division ratios can
be programmed from 128 to 159 and consumes 11mA under a 2.2V power supply, which
corresponds to 59.2% power reduction compared to the prior art.||en