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dc.contributor.advisorDai, Foster
dc.contributor.authorRay, Mark
dc.date.accessioned2009-03-23T15:51:10Z
dc.date.available2009-03-23T15:51:10Z
dc.date.issued2009-03-23T15:51:10Z
dc.identifier.urihttp://hdl.handle.net/10415/1614
dc.description.abstractThis paper presents the analysis, design, simulation, and test results for a Fractional-N PLL frequency synthesizer. The synthesizer is designed to cover multiple frequency bands, require low power, and have low noise. Detailed analysis is presented on loop dynamics, stability, and noise. All components in the circuit are designed for low noise and low power. For example, The Multi-Modulus Divider (MMD) is implemented such that it has the minimum number of gates and the lowest power consumption. The division ratios can be programmed from 128 to 159 and consumes 11mA under a 2.2V power supply, which corresponds to 59.2% power reduction compared to the prior art.en
dc.rightsEMBARGO_NOT_AUBURNen
dc.subjectElectrical Engineeringen
dc.titleA Low Power, Low Noise Phase Locked Loop MMIC for Ku- and X-Band Applicationsen
dc.typethesisen
dc.embargo.lengthNO_RESTRICTIONen_US
dc.embargo.statusNOT_EMBARGOEDen_US


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