Analysis and Implementation of Built-In Self-Test for Block Random Access Memories in Virtex-5 Field Programmable Gate Arrays

Abstract

In order to ensure the proper operation of the embedded Block Random Access Memories (BRAMs) in Xilinx Virtex-5 Field-Programmable Gate Arrays (FPGAs) a dependable and resource efficient test is needed so that the integrity of the memory can be guaranteed in a timely manner. The approach that is described in this thesis is based on a Built-In Self-Test (BIST) approach initially proposed by Garimella for Xilinx Virtex-1 and Virtex-2 FPGAs. It was later expanded upon by Milton for Xilinx Virtex-4 FPGAs. The work was continued by Garrison for Virtex-4 in order to improve BIST generation and execution time. Garrison also proposed a design for BRAM BIST for Virtex-5 FPGAs. Garrison’s proposal for Virtex-5 FPGAs is expanded upon and implemented in this thesis.