Built-In Self-Test Configurations for Field Programmable Gate Array Cores in Systems on Chip
Type of DegreeThesis
DepartmentElectrical and Computer Engineering
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Built-In Self-Test configurations for the logic and routing resources present in the Field Programmable Gate Array core of a System-on-Chip is presented in this Thesis. These configurations completely test the Programmable Logic Blocks and Programmable Routing Resources present in the Field Programmable Gate Array Core. A vendorspecific CAD tool, Atmel System Designer software suite, is used in conjunction with custom design automation tools to generate a complete set of logic and routing BIST configurations for any size Atmel AT94K series FPGA core as well as any size Atmel AT40K series FPGA.