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Built-In Self-Test Configurations for Field Programmable Gate Array Cores in Systems on Chip


Metadata FieldValueLanguage
dc.contributor.advisorStroud, Charles
dc.contributor.advisorNelson, Victoren_US
dc.contributor.advisorSingh, Aditen_US
dc.contributor.authorHarris, Jonathanen_US
dc.date.accessioned2008-09-09T22:33:44Z
dc.date.available2008-09-09T22:33:44Z
dc.date.issued2004-12-15en_US
dc.identifier.urihttp://hdl.handle.net/10415/1028
dc.description.abstractBuilt-In Self-Test configurations for the logic and routing resources present in the Field Programmable Gate Array core of a System-on-Chip is presented in this Thesis. These configurations completely test the Programmable Logic Blocks and Programmable Routing Resources present in the Field Programmable Gate Array Core. A vendorspecific CAD tool, Atmel System Designer software suite, is used in conjunction with custom design automation tools to generate a complete set of logic and routing BIST configurations for any size Atmel AT94K series FPGA core as well as any size Atmel AT40K series FPGA.en_US
dc.language.isoen_USen_US
dc.subjectElectrical and Computer Engineeringen_US
dc.titleBuilt-In Self-Test Configurations for Field Programmable Gate Array Cores in Systems on Chipen_US
dc.typeThesisen_US
dc.embargo.lengthNO_RESTRICTIONen_US
dc.embargo.statusNOT_EMBARGOEDen_US

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